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Pull requests: llvm/circt

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278 Open 7,961 Closed
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Pull requests list

[FIRRTL][InferDomains] Add skip-domain option to selectively skip domain checking
#10887 opened Jul 22, 2026 by uenoku Member • 2/2 Loading…
7
[FIRRTL][InferDomain] Fix null pointer dereference
#10886 opened Jul 22, 2026 by uenoku Member • 1/2 Loading…
1
3
[FIRRTL] Rework ModuleInliner: pointer-identity hierpath contexts FIRRTL Involving the `firrtl` dialect
#10880 opened Jul 21, 2026 by dtzSiFive Contributor Loading…
10
18
[FIRRTL][Seq] Add explicit clock edge
#10879 opened Jul 21, 2026 by Clo91eaf Contributor Loading…
12
[circt-bmc] Lower BMC trace markers to runtime callbacks
#10876 opened Jul 21, 2026 by 5iri Contributor Loading…
3
[ImportVerilog] Support $past(expr, number_of_tick) and error explicitly on unhandled sampled-value arities
#10868 opened Jul 20, 2026 by VecoMr Member Loading…
1
[Datapath] Signed Multiplication via Booth Encoding
#10867 opened Jul 20, 2026 by cowardsa Contributor Loading…
4
[ImportVerilog] Support %p format specifier for int, string, and struct
#10865 opened Jul 20, 2026 by VecoMr Member Loading…
2
[MooreToCore] Lower $realtobits/$bitstoreal/$shortrealtobits/$bitstoshortreal builtins to arith.bitcast
#10864 opened Jul 19, 2026 by VecoMr Member Loading…
2
[MooreToCore] Lower moore.null and handle comparisons to LLVM ptr ops
#10863 opened Jul 19, 2026 by VecoMr Member Loading…
1
[PyRTG] Thread a CodeGenContext through for CLI-configurable settings RTG Involving the `rtg` dialect
#10861 opened Jul 18, 2026 by maerhart Member Loading…
1
[ImportVerilog] Lower intra-assignment repeated event controls
#10860 opened Jul 17, 2026 by AmurG Contributor Loading…
1
[LLHD] Leave non-suspending recursive calls un-inlined in InlineCalls
#10859 opened Jul 17, 2026 by AmurG Contributor Loading…
1
[HW] Materialize constant bitcasts as aggregate constants
#10858 opened Jul 17, 2026 by AmurG Contributor Loading…
1
[ImportVerilog] Support the %v strength format specifier
#10857 opened Jul 17, 2026 by AmurG Contributor Loading…
1
[HW] Fold struct_extract of a bitcast of a constant
#10856 opened Jul 17, 2026 by AmurG Contributor Loading…
1
[Arc][LLHD] Make InsertRuntime and Mem2Reg emission order deterministic
#10855 opened Jul 17, 2026 by AmurG Contributor Loading…
1
[HW] Add aggregate constant support to bitcast fold HW Involving the `hw` dialect
#10854 opened Jul 17, 2026 by fzi-haxel Contributor Loading…
34
[MooreToCore] Implement ExtractRef for packed structs in LHS expressions
#10852 opened Jul 17, 2026 by AlviseDeFaveri Contributor • Draft
1
[PyRTG] Add Github CI workflow RTG Involving the `rtg` dialect
#10850 opened Jul 17, 2026 by maerhart Member • Draft
4
[Arc][LLHD][Moore] Simulation lowering robustness: module-level LLHD signals in LowerState, false comb-loop splitting, Deseq multi-driver soundness
#10839 opened Jul 16, 2026 by AmurG Contributor Loading…
2
[ImportVerilog][MooreToCore] Frontend completeness batch: severity tasks, packed-aggregate selects/case, interface-port arrays, OOB extract_ref
#10838 opened Jul 16, 2026 by AmurG Contributor Loading…
2
[FIRRTL] Support constants in InferDomains
#10837 opened Jul 16, 2026 by seldridge Member • Draft
1
[FIRRTL] Generalize walkDrivers
#10836 opened Jul 16, 2026 by seldridge Member Loading…
1
[Probe] Add read-only probe dialect and HW port restrictions
#10818 opened Jul 11, 2026 by nanjo712 Contributor Loading…
5
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